Design Of Low Power &Energy Proficient Pulse Triggered Flip- Flops

In this paper, pulse-triggered flip-flop types which are bidirectional elements in sequential logic circuits were designed. Initially, the pulse generation control logic is removed from the critical path to facilitate a faster discharge operation. Following low-power techniques are implemented, such as conditional capture, conditional precharge, conditional discharge, conditional data mapping, clock gating technique and SAL technique. Among all the mentioned techniques, SAL technique is the best one to avoid internal switching activities to reduce power dissipation, and also proposed circuit can be estimated as free of glitches. This paper explores the energy-delay space of widely referred flipflops in a 180nm CMOS technology.